Orżanowski: The Delay-Locked Loop technique for temperature stabilization of internal delays of CMOS FPGA devices, Electronics Letters, Vol. 36, No. 14, 2000, pp. 1184–1185 R. Szplet, J. Kalisz, R. Szymanowski: Interpolating time counter with 100-ps resolution on a single FPGA device, IEEE Transactions on Instrumentation and Measurement, Vol. 49, No. 4, August 2000, pp. 879–883 J. Kalisz, R. Szplet, R. Pełka, A. Poniecki: Single-chip low-cost time counter for distance measurements with 3 cm resolution, Journal of Optics, Vol. 29, 1998, pp. 199–205 J. Kalisz, R. Szplet, R. Pełka: Single-chip interpolating time counter with 200-ps resolution and 43-s range, IEEE Transactions on Instrumentation and Measurement, Vol. 46, No. 4, August 1997, pp. 851–856 R. Pełka, J. Kalisz, R. Szplet: Nonlinearity correction of the integrated time-to-digital converter with direct coding, IEEE Transactions on Instrumentation and Measurement, Vol. 46, No. 2, April 1997, pp. 449–452 J. Kalisz, R. Szplet, J. Pasierbinski, A. Poniecki: Field-Programmable-Gate-Array-Based Time-to-Digital Converter with 200-ps Resolution, IEEE Trans. on Instrum. and Measurement, Vol. 46, No. 1, February 1997, pp. 51–55 J. Kalisz, R. Szplet: Time-to-digital converter with direct coding and 100-ps resolution, Electronics Letters, Vol. 31, No. 19, 1995, pp.
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